A three-dimensional memory array has a plurality of layers of memory cells stacked vertically above one another and above a single substrate of an integrated circuit. U.S. Pat. No. 6,034,882 to Johnson et al., which is assigned to the assignee of the present invention, describes one such three-dimensional memory array. Support circuitry for the three-dimensional memory array can be formed in the substrate at least partially under the three-dimensional memory array. Although there are many advantages associated with three-dimensional memory arrays, improvements that allow a three-dimensional memory array to be used in a variety of applications are desired.
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims.
By way of introduction, the preferred embodiments described below relate to a monolithic integrated circuit comprising a three-dimensional memory array having a plurality of layers of memory cells stacked vertically above one another and above the substrate of the integrated circuit. Support circuitry for the three-dimensional memory array is formed in the substrate at least partially under the three-dimensional memory array and defines open area in the substrate under the three-dimensional memory array. In one preferred embodiment, one or more memory arrays are formed at least partially in the open area under the three-dimensional memory array, while in another preferred embodiment, logic circuitry implementing one or more functions is formed at least partially in the open area under the three-dimensional memory array. In yet another preferred embodiment, both one or more memory arrays and logic circuitry are formed at least partially in the open area under the three-dimensional memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
The preferred embodiments will now be described with reference to the attached drawings.